The NC676 no-clean solder paste is a new generation halide-free, rosin-based chemistry designed to provide a previously unseen level of repeatability and consistency to the printing process. This paste offers an excellent open time, extended abandon time and good soldering activity with all surface finishes.
NC676 meets or exceeds the requirements for ANSI/J-STD -004, -005 as well as all Bellcore test criteria for pastes. Residues left behind are clear and maintain a virtually indefinite pin probability life.
Material Safety Data Sheets (MSDS)
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Stencil aperture design and stencil quality are major factors in achieving excellent print consistency with any no clean solder paste. SMT stencils for printed circuit boards are recommended for optimal print performance, and can be custom designed to minimize and improve the yields of any process. Some general stencil aperture design guidelines follow:
A 0.001” reduction (L & W) to minimize bridging and create proper gasketing between the stencil and SMT pad
A 0.002” reduction (L & W) for water washable and a 0.002” reduction (L & W), with “U-shaped” home-plates, for no clean to minimize mid-chip solder beads.
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A linear ramp of 0.7°C to 2.0°C C/second is suggested to gradually remove the solvents and other volatile components from the printed circuit boards in the no clean solder paste. This also helps in minimizing solder balls, beading and bridging from hot slump. A linear ramp also helps minimize depletion of flux activity which can occur with excessive temperature, preheat times, and at very high reflow temperatures.
A profile with a soak between 200-210°C for less than 20 seconds can be used to reduce void formation on BGA and CSP devices. (Request FCTA’s profile guide to void reduction). While a linear profile typically does not produce tombstoning, a short 10-20 second dwell prior to transitioning into the liquidus point of the solder, and minimizing the QR between soak and liquid temperatures will help minimize tombstoning if experienced.
A cooling rate of 2°C-3°C per second is typical for most SN62 and SN63 applications. These parameters should be utilized to insure a fine grain solder structure and minimal IMC layer